1. Field of the invention
The present invention relates to a variable delay device. More specifically, the present invention relates to a variable delay device which is utilized as an analog IC delay line.
2. Description of the prior art
Up to now, there is a variable delay device which is constructed by using a C-MOS inverter. The C-MOS inverter has a transfer delay time of approximately few nanoseconds for each stage, and therefore, if the number of stages of the C-MOS inverter is increased, it is possible to obtain a delay time equal to the number of stages. The delay time of the C-MOS inverter can be adjusted by a driving voltage which is applied to the C-MOS inverter. In general, a control characteristic representative of a relationship between the driving voltage and the delay time becomes a non-linear characteristic as shown in FIG. 6.
In such a variable delay device, it becomes difficult to properly control the C-MOS inverter because the control characteristic largely varies due to dispersions or variations of temperature, circuit components and etc. Accordingly, there was a problem that a characteristic of the variable delay device does not become stable.